Conventional flash memory products employing floating gate technologies, where the memory state is represented by the charge stored in an insulated, but conducting layer between the control gate electrode and the device channel region, typically use programming voltages (i.e., writing and erasing) of 10V or higher. Because of the necessity of providing high voltage levels for floating gate memory operation, integration of floating gate memories with complementary metal oxide semiconductor (CMOS) is problematic. First, present CMOS power supplies (Vdd) are approaching 1V. At these low supply voltages, it is difficult to provide high voltage levels necessary for floating gate operation—even with the use of charge-pumping circuits. Presently, one is forced to provide a separate high voltage supply for floating gate memories, e.g., 3.3V, and the use of charge-pumping circuitry, in addition to a lower voltage supply source for any CMOS logic associated with the chip. For mobile applications, the high supply voltages necessary for conventional floating gate memories severely limit the battery life. Moreover, there is a severe cost penalty of integrating floating gate memories with CMOS—it is estimated that as many as nine (9) additional lithography steps may be necessary.
Randomly-accessible semiconductor-oxide-nitride-oxide-semiconductor (SONOS) are also referred to as metal-oxide-nitride-oxide-semiconductor (MONOS); note that the terms SONOS and MONOS denote basically the same type of memory cell except that polysilicon, is used as the SONOS gate conductor and a metal is used as the MONOS gate conductor) memory, is considered a viable replacement to floating gate memories due to the moderate operating voltages these memories employ, e.g., approximately 5V. In such memory cells, the memory state is represented by the charge stored in an insulator layer located between the control gate electrode and the device channel region. Depending on the programming conditions of the memory cells, it may be possible, for example, to lower the high voltage supply from 3.3V to 1.8V or even do away with the separate power supply altogether, thereby prolonging battery life. In addition, since SONOS memories typically utilize uniform tunneling for programming, reliability problems usually associated with floating gate memories, such as hot hole injection, are avoided.
However, SONOS cells are not immune to scaling concerns. The moderate voltages needed for programming put limits on the transistor design one can employ. Short-channel effects, including punch-through, can easily occur even at these voltages, if the device channel lengths are too short. Increasing channel doping concentrations to deter punch-through can lead to lower junction breakdown and destruction of any memory capability.
The scaling of SONOS memory cells has been limited to planar devices that are typically formed in bulk semiconductor substrates. The select gate and memory gate are typically formed separately and the cell sizes of these types of cells are usually large. Recently, a SONOS planar bit cell with a 0.157 μm2 cell size designed in 90 nm groundrules has been reported. See, for example, C. T. Swift, G. L. Chindalore, K. Harber, T. S. Harp, A. Hoefler, C. M. Hong, P. A. Ingersoll, C. B. Li, E. J. Prinz, J. A. Yater; “An embedded 90 nm SONOS nonvolatile memory utilizing hot electron programming and uniform tunnel erase,” IEDM Tech. Dig., pp. 927-930, December 2002. Although smaller in size, the planar cell has its limits as the channel length may be more difficult to scale in the forthcoming generations. In addition, the planar SONOS memory gate must be constructed separately from any CMOS gate process. Additional four (4) masks are required above and beyond the CMOS process to create the prior art SONOS cell array. Due to the necessity of separating the SONOS memory gate from CMOS processing, integration with high-performance CMOS can become costly.
In view of the above, there is a need for providing a method to integrate SONOS cells with SOI logic. Indeed, integration of planar SONOS cells on SOI is extremely difficult                the body of the planar devices are usually ‘floating’ and channel lengths tend to be relatively short rather than long (to avoid making fully depleted devices that are difficult to control). These imposed constraints make the fabrication of planar SONOS cells virtually impossible on SOI substrates.        
Thus, it would be beneficial to NVRAM technology if there could be a way of integrating SONOS on SOI where one can take advantage of utilizing high performance SOI logic devices together with the non-volatility of the SONOS memory cell.